About
This course entails analysis and design of phaselocked loop (PLL) architectures and circuits. Emphasis will be on fundamental understanding, design intuition, and implementation of PLLs in modern-day CMOS processes.
Topics include charge-pump phase-locked loops, noise properties of PLLs, integer/fractional-N PLLs, digital PLLs, delay-locked loops, and injection-locked clock multipliers. Supply noise mitigation techniques will be covered in detailclock and data recovery circuits.
Objectives
The primary objectives of the course are as follows:
- Understanding of basic and advanced PLL architectures
- Modelling of PLLs
- Exposure to circuit design of building blocks
- Provide design intuitionClock and data recovery (CDR) architectures
- Identification and mitigation of the impact of supply noise
- Exposure to practical problems of PLL’s CDRs and their solutions, through case studies.
Who can Attend?
The programme is open to the Faculty and Ph.D scholars/PG students of Electronics and Communication Engineering and allied disciplines. Industry personnel working in the concerned/allied discipline can also attend.
How to Apply?
- A filled application form in the prescribed format duly signed and sponsored by appropriate authorities (along with payment details) should send scanned application form & proof for Fee paid details through email to patri@nitw.ac.in.
- Interested candidates can apply online by clicking here.
- Also, the original hard copies of the application form & proof for Fee paid details must be submitted at registration desk on first day of reporting.
- The selection status will be intimated only through mail.
- Selection will be done based on firstcum-first-serve basis and the confirmed candidates will be notified immediately.
- The maximum number of participants will be 50 (Fifty).
- The Last date for Application with fee is 10th December 2019.
Contact
Phone Number: 8332969357
Email ID: patri@nitw.ac.in
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